|
General Description |
A7103A is a very easy-to-use CMOS RF transceiver for sub 1GHz license free ISM band (315/434MHz). It is a FSK/ASK single chip RF transceiver with high sensitivity receiver (-110dBm @ 2.4Kbps, 433.92MHz ASK, -106dBm @ 2.4Kbps, 433.92MHz FSK) as well as 4-steps programmable power amplifier (max. 10dBm @ 315 / 434MHz). This device integrates a double balanced image reject mixer, low IF frequency (424KHz) architecture, IF filter, I/Q limiter with RSSI generation, as well as a fully VCO and PLL synthesizer. A7103A's carrier frequency FRF is determined by the frequency of the reference Xtal FXTAL. The integer-N PLL synthesizer ensures that each RF value, ranging from 310 MHz to 315.5 MHz and 430 MHz to 438 MHz with PLL steps of 848KHz, can be achieved. This is done by using a Xtal as a reference frequency according to: FRF = FXTAL x N / 2R, where N is the PLL feedback divider ratio and R is Xtal divider to support 13.5732MHz crystal. Besides, A7103A supports AIF (Auto IF) function, user has no need to consider IF offset between TX and RX, but, use this formula ( FRF = FXTAL x N / 2R ) directly to calculate radio frequency in both TX and RX site. A7103A supports ASK data rate from 1K to 10Kbps and FSK from 1K to 20Kbps which is determined via external capacitors applied on data filter and data slicer. In FSK modulation, this device’s Fdev (frequency deviation) is controlled by Xtal detuning of series an external capacitor (typical 75pF for ± 12.5KHz ). However, this capacitor is not necessary in ASK modulation. For easy-to-use, A7103A has only two control registers, register 0 and 1. MCU can configure two registers via 3-wire SPI bus. In addition to SPI control mode, A7103A has a special mode called HW control mode. In HW control mode, user just needs to apply pin settings. Then radio control is done (register 0 and register 1 are in default values). No matter HW or SPI control mode, A7103A is very easy to use by a low cost MCU or encoder/decoder. Those features are all integrated in a small SSOP 24 pins package. For packet handling, there is no FIFO inside A7103A. Hence, in TX mode, MCU or Encoder just delivers the defined packet (preamble + sync word + payload) to TX_DATA pin. Then, in RX mode, MCU or Decoder can receive the packet (preamble + sync word + payload) from RX_DATA pin. Be aware that A7103A needs different preamble formats between ASK and FSK in order to get the best RX sensitivity. |